The present invention relates generally to a semiconductor device and, more particularly, to a semiconductor integrated circuit device having a capacitor formed under a bonding pad.
In general, the wafer area (i.e., chip area) occupied by a VLSI (very large scale integration) device is gradually increasing. More particularly, as the capacitance of a memory semiconductor integrated circuit increases and a plurality of function blocks (or chips) for performing various functions are integrated into one, the chip area of the VLSI device continuously increases.
FIG. 1 is a diagram illustrating a conventional semiconductor integrated circuit 1 (hereinafter xe2x80x9cICxe2x80x9d or xe2x80x9cchipxe2x80x9d). The chip 1 includes a plurality of bonding pads 12 arranged therein. Power wiring 14 supplies external supply voltage to the interior of the chip 1. Since the power wiring 14 is generally made of metal, the chip area occupied by the power wiring 14 is selectively greater than that occupied by other signal wiring. The plurality of bonding pads 12 connect the chip interior to the exterior thereof. The bonding pads 12 are electrically connected to corresponding package pins (not shown). The power wiring 14 is arranged inside the chip 1 as shown in FIG. 1. To simplify the illustration, ground voltage is not shown. The power wiring 14 occupies most of the area of the chip 1. The bonding pads 12 also occupy a significant area of the chip 1. In general, a semiconductor integrated circuit is not arranged adjacent to an area where the bonding pads 12 are formed.
In order to provide many chips in the same wafer, it is necessary to efficiently reduce a chip area which is continuously increasing.
An object of the present invention is to provide a semiconductor integrated circuit device having a capacitor formed under a bonding pad.
Another object of the present invention is to provide a semiconductor integrated circuit device having a power wiring structure arranged under a bonding pad.
According to a first aspect of the present invention, a semiconductor device includes a semiconductor substrate having a main surface. A bonding pad is formed on the main surface. A multi-layer wiring structure is disposed between the main surface and the bonding pad. The multi-layer wiring structure includes a first wiring layer, a second wiring layer, and an interlayer insulating film therebetween.
According to a second aspect of the present invention, the first layer, the second layer, and the interlayer film form a capacitor disposed under the bonding pad.
According to a third aspect of the present invention, widths of the first and the second wiring layers are respectively equal to and wider than a width of said bonding pad.
According to a fourth aspect of the present invention, the first wiring layer is formed by using ground wiring for receiving an external ground voltage, and the second wiring layer is formed by using power wiring for receiving an external supply voltage.
According to a fifth aspect of the present invention, the capacitor is used to stabilize ground voltage noise or supply voltage noise.
According to sixth aspect of the present invention, a semiconductor device includes a semiconductor substrate having a main surface. A plurality of bonding pads are formed on an area of the main surface. A first conductive layer having a plurality of first conductive patterns is formed on the main surface and arranged along the area. A second conductive layer having a plurality of second conductive patterns is formed between the main surface and the first conductive layer and arranged along the area to overlap with the first conductive patterns. An insulating layer is disposed between the first and the second conductive layers.
According to a seventh aspect of the present invention, a semiconductor device includes a semiconductor substrate having a main surface. A plurality of bonding pads are formed on an area of the main surface. A first wiring layer is arranged between the main surface and the pads and grown along the area. A second wiring layer is arranged between the main surface and the first wiring layer and along the area. An insulating layer is arranged between and in contact with the wiring layers.
According to an eighth aspect of the present invention, the first wiring layer has a plurality of via holes under the bonding pads to reduce stress generated when the bonding pads are bonded to external package pins.
According to a ninth aspect of the present invention, a semiconductor device having a plurality of bonding pads includes a conductive semiconductor substrate having a main surface. A conductive active region is formed in the semiconductor substrate. An insulating layer is formed on the main surface. A conductive layer is formed on the insulating layer. The conductive active region, the insulating layer, and the conductive layer are formed below the plurality of bonding pads.
According to a tenth aspect of the present invention, the active region is simultaneously formed when source/drain regions of a metal oxide semiconductor transistor are formed, and the conductive layer is simultaneously formed when a gate electrode of the transistor is formed.
According to an eleventh aspect of the present invention, a semiconductor device having a plurality of bonding pads includes a conductive semiconductor substrate having a main surface. A conductive layer has a plurality of conductive patterns formed on the main surface and arranged along an area having the bonding pads. An insulating layer is formed between the main surface and the conductive layer. A plurality of conductive active regions are formed in the semiconductor substrate along the bonding pad region.